As semiconductor devices are becoming more highly integrated and compact, the scale-down of transistors used in semiconductor devices is accelerated. However, these transistors are facing the problems in that the channel length becomes shorter and an electrical short between terminals like a punch-through takes place.
Therefore, recently, for the purpose of preventing a bird's beak and the punch-through which afflict conventional methods such as local oxidation of silicon (hereinafter referred to as “LOCOS”) and SEPOX (selective polysilicon oxidation), a new method called an STI method by which a shallow trench is formed has been introduced.
Referring to FIG. 1a, a pad oxide layer 12 and a pad nitride layer 13 are sequentially formed on a semiconductor substrate 11. Next, a photoresist is coated on the resulting substrate and an exposure process for the photoresist is carried out by using a reticle. The photoresist is then etched to form a photoresist pattern. After some part of the pad nitride layer 13 in which an STI will be formed is etched by using the photoresist pattern as a mask, the photoresist pattern is removed through a strip process. Similarly, the pad oxide layer 12 is etched by using the pad nitride layer 13 as a mask. By using the patterned pad oxide layer 12 and pad nitride layer 13 as a hard mask, the semiconductor substrate 11 is etched to the required depth to complete a trench 14.
Referring to FIG. 1b, after the etching process, the trench 14 has sharp edges that can cause the centralization of a voltage applied to a gate electrode to be formed later. To prevent this, a thermal oxide layer 15 is formed with a thickness of 200 Å by carrying out a thermal treatment of the trench 14 so that the edges become blunt.
Referring to FIGS. 1c and 1d, after the trench 14 is filled by an oxide layer 16, the resulting surface is planarized by a CMP (chemical mechanical polishing). As the residual pad nitride layer 13, i.e. the hard mask, and the pad oxide layer 12 are removed, an STI 16a is finally formed to isolate each unit device.
However, referring to FIG. 2a, if the STI is formed by the known method described above, CD (critical dimension) of the STI on the edge of the substrate as well as its depth becomes smaller. Furthermore, referring to FIG. 2b, as the insulation layer on the edge 22 of the substrate has a more even surface than its center 21, an etch rate becomes worse during the planarization process, so that the residual insulation layer 23 remains on the hard mask and obstructs the removal of the hard mask during the subsequent wet etch for the hard mask.